The present invention generally relates to integrated circuits, and more particularly to fabricating semiconductor structures having self-aligned contacts.
Contacts may be formed in order to make electrical connections to a semiconductor device. Contacts to a source region or a drain region (referred to collectively as “source-drain regions”) of the semiconductor device may be referred to as CA contacts. CA contacts may be distinguished from CB contacts which may form an electrical connection to the gate of a semiconductor structure. In some cases, the source-drain regions must remain electrically isolated from the gate terminal in order to maintain functionality of the semiconductor device. In such situations, a short circuit between the source-drain regions and the gate may damage the semiconductor device.
A CA contact may be formed in a contact hole etched in an interlevel dielectric (ILD) layer deposited over the semiconductor device, and therefore may be surrounded by the ILD layer. As a result of device scaling, self-alignment techniques are becoming widely used to relax alignment requirements and improve control of critical dimensions. A self-alignment technique commonly used may include a self-aligned contact (SAC) etch, in which a pair of adjacent gates may be used to align a recess created in the ILD layer.